Phasor Electronics Design
	Electronic circuit and system design consulting services
	Employment Projects

This page describes projects that I worked on professionally in positions as Sr. Hardware Designer, Technical Lead, and Project Engineer before I started my own company.

Toby Haynes
Owner, Phasor Electronics Design

Product Definition and Managing Development Projects 

As well as the hands-on hardware design work described below, I have defined and overseen the engineering development of a number of projects:

	A/D PMC module. A high speed 12-bit A/D module that can directly digitize radio signals up to 30 MHz. Used to provide sampled wideband radio signals to digital tuners.
	Quad Digital Tuner Module. An I/O module for a TMS320C6x DSP system that includes four Harris HSP50214 digital down-converters to tune and demodulate radio signals.
	DSP Modules. Circuit board modules that include 1 and 2 TMS320C44 60 MHz DSP's and static memory. These are used as building blocks for parallel-processing DSP systems.
	Single Digital Receiver Module. A circuit board module that includes a high-speed 12-bit A/D converter, digital down-converter, and TMS320C44 DSP. It can directly tune and demodulate radio signals up to 30 MHz.
	Acoustic Echo Canceller Module. A Motorola 24-bit DSP56002 is combined with an audio CODEC and memory on an IndustryPack (IP) module.
	DSP IndustryPack Module. This custom DSP56002 module is installed on a VME system controller board. It performs signal processing to implement a CDPD radio modem.

Data Converters for Software-Defined Radio. These cards are parts of systems for digital processing of intermediate-frequency signals up to 70 MHz in many-channel software-defined radio (SDR) transceivers. They provide multi-channel A/D and D/A conversion at over 200 megasamples per second. Features include a phase-locked sampling clock, time-stamping, and multi-card synchronization. I specified and designed these cards and was involved in the architectural definition and specification of the rest of the system.

Multichannel Software-Defined Radio Digitizer. This PCI card filters and coherently digitizes six intermediate-frequency signals with over 90 dB of spurious-free dynamic range. Its sampling clock is phase-locked to an external reference, and the card time-stamps data, with time input from an external GPS receiver. It has two signal processors and a large dynamic memory store. I specified the board and designed the analog input, A/D, PLL, and time-stamping circuitry.

Software-Defined Radio Receiver Library. Developed in C for the TMS320C40 processor, this library includes functions for channel filtering, demodulation of AM, FM, SSB and CW signals, baseband filtering, and automatic gain control. I designed and implemented the algorithms. Matlab was used for the design of digital filters for this library.

Digital Drop Receiver. This set of two circuit board modules is used to build multichannel software-defined radio (SDR) receivers.

The high speed A/D module (right) digitizes the IF signal, from 0.01 to 30 MHz, at 70 megasamples/sec. Many different radio signals may be present in the sampled digital IF, which is distributed to many Digital Down Converter (DDC) modules through a 1.4 gigabit/sec coaxial serial link.

On each DDC module (left), the sampled IF is applied to four narrow-band DDC chips, each of which "channelizes" one radio signal. This involves converting the signal to baseband I and Q components, digital filtering to establish the channel bandwidth, and decimating to reduce the sample rate. Two TMS320C40 DSP's operate on the baseband samples to demodulate four radio signals simultaneously.

My work included specification, estimation and planning, and project lead of a team of 3. I designed sections of the DDC module, including the 1.4 gigabit/sec PECL serial interface and 70 MHz CMOS interface to the DDC chips, and characterized performance of the A/D module. I development a library of C functions to control the A/D module and DDC chips, with example programs to demonstrate down-conversion and spectrum analysis.

Autonomous Precision Approach and Landing System 

Developed by Lockheed-Martin, this VME-based avionics system prototype navigated an aircraft to landing using synthetic-aperture radar, GPS, and inertial sensors. Working for a subcontractor, I was involved in the design of the "Digital Electronics Unit" (DEU), which interfaced with a radar transceiver, inertial measurement unit, radar altimeter, and other avionics. APALS performed hundreds of successful landings during test flights. The customer was very pleased with the DEU performance and reliability.

Before approach to an airport, APALS uses GPS to determine it's approximate position. It then makes synthetic-aperture radar (SAR) images of the ground every few seconds and correlates these with stored maps to accurately determine the aircraft position and velocity. A radar altimeter gives accurate altitude. Between SAR correlation's, aircraft position is updated based on data from an Inertial Measurement Unit (IMU). During landing, aircraft navigation is independent of GPS satellites or ground stations. The system presents information to the pilot on a conventional Instrument Landing System display and may interface to an autopilot for automatic landing.

The following functions were integrated into the DEU:

SPARC system controller
Four C40 DSP boards
Hard drives
Direct Digital Synthesizer (DDS) for the SAR transmitter
GPS receiver
Custom DSP board
Custom I/O board
Custom 6U VME backplane, chassis, power supplies
Custom Low-Noise Power Supply for the DDS

Our team of 4 specified, built, and delivered the DEU hardware in 8 months. My work included assistance with estimation and planning, specification of the DEU cards, chassis, and backplane, technical liaison with our customer and the backplane and chassis subcontractors, and acceptance test planning and procedures. I designed the analog and discrete I/O circuitry, radar I/Q digitizer, low-noise power supply, and a test-jig PCB. I wrote test software in TMS320C40 'C' to exercise the circuitry, made performance measurements, and did acceptance testing of analog and RF sections of the DEU.

Custom DSP Board
C40 DSP, radar I/Q digitizers, radar frequency-hop controller, serial and SCSI interfaces

Custom I/O Board
RS-232 and ARINC serial, analog & discrete 28V digital I/0, audio generator

Rear Panel of Custom Chassis

DSP Module with DRAM. This board combines very large dynamic memory with a DSP, for image processing and other applications that require large data storage. A 50 MHz TMS320C40 DSP has access to 128 megabytes of DRAM. Static RAM is also provided for code storage. I wrote specifications and designed the DRAM controller section.

Audio Encoder/Decoder. Developed for the audio section of an ISDN video conferencing system, this IP module performs G.711/722/728 speech compression using a 40 MHz floating-point TMS320C31 DSP. I wrote the specifications and designed and tested the hardware.

GMSK Modem Transition Module. This VME rear panel transition module board provides analog I/O for interface to a radio transceiver. It works with a DSP IndustryPack module to form the modem in cellular radio base stations for CDPD data communication. I served as project leader, wrote specifications, and designed the analog I/O transition module.

DSP Video Processing Board. This PC image-processing board uses a TMS34020 graphics processor to capture video from a camera and display video on a CRT. A TMS320C31 DSP is used to process images stored in the frame buffer. A custom high-speed bus allows this card to connect to a mutli-DSP card for additional processing. I wrote specifications and designed all of the hardware.

Base Station Controller for Wireless Data. I served as a hardware designer on the development team for the 2100 Base Station Controller. This VME-based system with a 68000 processor and a 56001 DSP controlled a radio transceiver and served as the modem in base stations for Motorola's digital radio dispatch and data network products. I wrote detailed specifications for the cards and chassis, designed DSP and I/O circuitry, wrote test software, and performed accelerated life testing of the completed unit.

Video Controller Chips. I worked on single-chip ASIC implementations of IBM video controllers for PC's. As one of a 2-man team, I implemented the "Enhanced Graphics Adapter" in a 12,000 gate array (left). I was also on a team of 5 that implemented VGA in a 15,000 gate array (right). My contributions included specification, logic design, test vector generation, in-house and foundry simulations, and prototype testing and debugging.

(c) Phasor Electronics Design. Oct 2021